Alias-free tagged error correcting codes for machine memory operations
US12321230B2 · kind B2 · utility
0Cited by
1References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2023 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Feb 22, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Implicit Memory Tagging (IMT) mechanisms utilizing alias-free memory tags that enable hardware-assisted memory tagging without incurring storage overhead above those incurred by conventional tagging mechanisms, while providing enhanced data integrity and memory security. The IMT mechanisms enhance the utility of error correcting codes (ECCs) to test memory tags in addition to the traditional utility of ECCs for detecting and correcting data errors and enable a finer granularity of memory tagging than many conventional approaches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.