Patent · US Active

Incremental compilation for FPGA-based systems

US12321675B2 · kind B2 · utility

0Cited by

1References

18Claims

0Family size

Assignee

SYNOPSYS, INC. · US

Inventors

Ying-Tsai Chang · Fremont, US
Kuen-Yang Tsai · Zhudong, TW
Ryan Zhang · Shenzhen City, CN
Meng-Chyi Lin · Taoyuan, TW

Key dates

Filing date	Mar 14, 2022
Grant date	Jun 3, 2025
Priority date	—
Expiry date	Nov 25, 2043

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/333
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments of the present disclosure relate to a system and method for incremental compilation. The method includes identifying a change to a portion of a circuit design. The circuit design without the change was previously compiled to an FPGA. The method also includes configuring a transactor of the FPGA to simulate the portion of the circuit design with the change and configuring the FPGA to use the transactor to simulate the portion of the circuit design with the change.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.