Full die and partial die tape outs from common design
US12321681B2 · kind B2 · utility
0Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2022 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Aug 30, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A chip design methodology and a set of integrated circuits that are taped out from a common design database are disclosed. The area of a full instance of the integrated circuit is defined, and one or more chop lines are defined to identify portions that will be removed for one or more partial instances. A variety of techniques and mechanisms are defined to permit the tape outs to occur from a common design database, so that the effort to tape out partial instances may be minimized beyond that to tape out the full instance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.