Compressed wallace trees in FMA circuits
US12321714B2 · kind B2 · utility
0Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2021 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Oct 5, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3892
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of an apparatus comprises one or more fractional width fused multiply-accumulate (FMA) circuits configured as a shared Wallace tree, and circuitry coupled to the one or more fractional width FMA circuits to provide one or more fractional width FMA operations through the one or more fractional width FMA circuits. Other embodiments are disclosed and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.