Apparatus and method with neural network computation scheduling
US12321733B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 1, 2022 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Apr 27, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a processor configured to generate each of intermediate representation codes corresponding to each of a plurality of loop structures obtained that corresponds to a neural network computation based on an input specification file of hardware; schedule instructions included in each of the intermediate representation codes corresponding to the plurality of loop structures; select, based on latency values predicted according to scheduling results of the intermediate representation codes, any one code among the intermediate representation codes; and allocate, based on a scheduling result of the selected intermediate representation code, instructions included in the selected intermediate representation code to resources of the hardware included in the apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.