Managing page buffer circuits in memory devices
US12322469B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2023 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Jun 14, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, circuits, and apparatus for managing page buffer circuits in memory devices are provided. In one aspect, a memory device includes a memory cell array, a page buffer circuit including a plurality of page buffers, and a cache data latch (CDL) circuit including a plurality of caches coupled to the plurality of page buffers through a plurality of data bus sections. The plurality of data bus sections are configured to be conductively connected together as a data bus for data transfer. Each data bus section corresponds to a page buffer in the page buffer circuit and is configured to conductively separate from at least one adjacent data bus section for data sensing in the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.