Method of manufacturing semiconductor devices and corresponding semiconductor device
US12322603B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 25, 2022 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Aug 20, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L24/82
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor chips are arranged on an elongated substrate and encapsulated by an insulating encapsulation. Electrically conductive formations and electrically conductive plating lines are plated on the insulating encapsulation using, for example, Laser Direct Structuring (LDS) or Direct Copper Interconnect (DCI) material. The electrically conductive plating lines include first transverse plating lines as well as second plating lines branching out from the first plating lines towards the electrically conductive formations. A first partial cutting step is then performed to form grooves which remove the first plating lines. An insulating material is dispensed in the grooves to encapsulate the end portions of the second plating lines. A second cutting step median along the groove and through the elongate substrate is performed to produce singulated semiconductor devices (such as “die pad up” Quad-Flat No-lead (QFN) packages). End portions of the second plating lines are encapsulated by the insulating material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.