Heterogeneous integration of radio frequency transistor chiplets having interconnection tuning circuits
US12322714B2 · kind B2 · utility
0Cited by
11References
18Claims
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Key dates
| Filing date | Oct 20, 2023 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Oct 20, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/6688
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic assembly has a host wafer having a first circuit including passive devices for the purpose of one of tuning or matching networks. Chiplets are placed in the cavities. At least one chiplet has a second circuit including at least one transistor or switch device and passive tuning circuits including at least one of a stabilization network, a gain boosting network, a power delivery network, or a low-noise network. Electrical interconnects between the chiplets and wafer electrically connect the first circuitry to the second circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.