Channel protection of gate-all-around devices for performance optimization
US12324207B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 2021 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | Oct 3, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/364
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A gate-all-around device includes a plurality of channel layers vertically stacked over a substrate, an inner spacer located between each of the plurality of channel layers, source/drain regions in contact with opposite ends of a first portion of the plurality of channel layers, and a first dielectric layer on opposite ends of a second portion of the plurality of channel layers located in a spacer region that is adjacent to the source/drain regions. A width of the first dielectric layer and the second portion of the plurality of channel layers is equal to a width of the inner spacer located between each of the plurality of channel layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.