Ruilong Xie
1,139Patents
32h-index
295Co-inventors
89Inventor score
Filing activity: Aug 8, 2011 → Oct 25, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10332963B1 | Uniformity tuning of variable-height features formed in trenches | Electricity | 326 | Active |
| US9111907B2 | Silicide protection during contact metallization and resulting semiconductor structures | Electricity | 172 | Active |
| US9412616B1 | Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products | Electricity | 109 | Active |
| US9947804B1 | Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure | Electricity | 91 | Active |
| US10192867B1 | Complementary FETs with wrap around contacts and method of forming same | Electricity | 82 | Active |
| US9847390B1 | Self-aligned wrap-around contacts for nanosheet devices | Electricity | 57 | Active |
| US9093467B1 | Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices | Electricity | 55 | Active |
| US9984936B1 | Methods of forming an isolated nano-sheet transistor device and the resulting device | Electricity | 55 | Active |
| US10014390B1 | Inner spacer formation for nanosheet field-effect transistors with tall suspensions | Electricity | 54 | Active |
| US9245885B1 | Methods of forming lateral and vertical FinFET devices and the resulting product | Electricity | 54 | Active |
| US10510620B1 | Work function metal patterning for N-P space between active nanostructures | Electricity | 54 | Active |
| US9991352B1 | Methods of forming a nano-sheet transistor device with a thicker gate stack and the resulting device | Electricity | 54 | Active |
| US9780208B1 | Method and structure of forming self-aligned RMG gate for VFET | Electricity | 49 | Active |
| US9397003B1 | Method for forming source/drain contacts during CMOS integration using confined epitaxial growth techniques | Electricity | 48 | Active |
| US9362181B1 | Methods of forming diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products | Electricity | 46 | Active |
| US10192819B1 | Integrated circuit structure incorporating stacked field effect transistors | Electricity | 45 | Active |
| US8524592B1 | Methods of forming semiconductor devices with self-aligned contacts and low-k spacers and the resulting devices | Electricity | 44 | Active |
| US10332803B1 | Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of forming | Electricity | 42 | Active |
| US8703557B1 | Methods of removing dummy fin structures when forming finFET devices | Electricity | 42 | Active |
| US9502518B2 | Multi-channel gate-all-around FET | Electricity | 40 | Active |
| US10256158B1 | Insulated epitaxial structures in nanosheet complementary field effect transistors | Electricity | 39 | Active |
| US9865704B2 | Single and double diffusion breaks on integrated circuit products comprised of FinFET devices | Electricity | 39 | Active |
| US9508604B1 | Methods of forming punch through stop regions on FinFET devices on CMOS-based IC products using doped spacers | Electricity | 38 | Active |
| US9716170B1 | Reduced capacitance in vertical transistors by preventing excessive overlap between the gate and the source/drain | Electricity | 38 | Active |
| US9536982B1 | Etch stop for airgap protection | Electricity | 37 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.