Stress layout optimization for device performance

US12324213B2 · kind B2 · utility

Assignee

• GLOBALFOUNDRIES U.S. Inc. · US

Inventors

• Dirk Utess · Dresden, DE
• Zhixing Zhao · Dresden, DE
• Dominik Martin Kleimaier · Dresden, DE
• Irfan Saadat · Abu Dhabi, AE
• Florent Ravaux · Maninghen-Henne, FR

Key dates

• Filing date: Mar 28, 2023
• Grant date: Jun 3, 2025
• Expiry date: Mar 28, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to a layout optimization for radio frequency (RF) device performance and methods of manufacture. The structure includes: a first active device on a substrate; source and drain diffusion regions adjacent to the first active device; and a first contact in electrical contact with the source and drain diffusion regions and which is spaced away from the first active device to optimize a stress component in a channel region of the first active device.