Tall bottom electrode structure in embedded magnetoresistive random-access memory
US12324358B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2021 |
| Grant date | Jun 3, 2025 |
| Priority date | — |
| Expiry date | May 21, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
Abstract
Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure is provided, the memory area interconnect structure comprising metal interconnects formed in the substrate. A metal line on a metal interconnect of the non-memory area interconnect structure is formed. A first dielectric layer on exposed surfaces of the non-memory area is formed. A hardmask is formed on the dielectric layer. A second dielectric layer is formed on exposed surfaces of the memory area. A bottom metal contact is formed in a trench, a bottom surface of the bottom metal contact on a top surface of a first metal interconnect of the memory area interconnect structure. A memory element stack pillar is formed on the bottom metal contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.