Bit line pre-charge circuit for power management modes in multi bank SRAM
US12327586B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2024 |
| Grant date | Jun 10, 2025 |
| Priority date | — |
| Expiry date | Feb 23, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for controlling a wake-up operation of a memory circuit. The memory circuit is configured to precharge the bit lines of a memory array sequentially during wakeup. A sleep signal is received by the first bit line of a memory cell and then a designed delay occurs prior to the precharge of a second complementary bit line. The sleep signal may then precharge the bit lines of a second memory cell with further delay between the precharge of each bit line. The memory circuit is configured to precharge both bit lines of a memory cell at the same time when an operation associated with that cell is designated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.