Method of RRAM write ramping voltage in intervals
US12327587B2 · kind B2 · utility
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14References
20Claims
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Key dates
| Filing date | Jun 2, 2023 |
| Grant date | Jun 10, 2025 |
| Priority date | — |
| Expiry date | Jun 2, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a resistive random access memory (RRAM) circuit and related method to limit current, or ramp voltage, applied to a source line or bitline of an RRAM array. The RRAM array has one or more source lines and one or more bitlines. A control circuit sets an RRAM cell to a low resistance state in a set operation, and resets the RRAM cell to a high resistance state in a reset operation. A voltage applied to a bitline or source line is ramped during a first time interval, held to a maximum voltage value during a second interval, and ceased after the second time interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.