Semiconductor package including redistribution substrate
US12327824B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2022 |
| Grant date | Jun 10, 2025 |
| Priority date | — |
| Expiry date | Aug 25, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/1094
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a lower semiconductor chip disposed on a lower redistribution substrate, lower solder patterns disposed between the lower redistribution substrate and the lower semiconductor chip, conductive structures disposed on the lower redistribution substrate, a lower molding layer disposed on the lower redistribution substrate and covering a top surface of the lower semiconductor chip, an upper redistribution substrate disposed on the lower molding layer and electrically connected to the conductive structures, an upper semiconductor chip disposed on the upper redistribution substrate, upper solder patterns disposed between the upper redistribution substrate and the upper semiconductor chip, and an upper molding layer disposed on the upper redistribution substrate and covering a sidewall of the upper semiconductor chip. The number of the conductive structures is greater than that of chip pads of the upper semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.