Layout of integrated circuit

US12328944B2 · kind B2 · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventors

• Ruei-Yau Chen · Shiwen, TW
• Wei Wang · Westborough, US
• Kun-Yuan Wu
• Chien-Fu Chen · Banluliao, TW
• Chen-Hsien Hsu · Dashulong, TW

Key dates

• Filing date: Nov 2, 2021
• Grant date: Jun 10, 2025
• Expiry date: Nov 24, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/974

Abstract

An integrated circuit layout includes a first and a second standard cells abutting along a boundary line. The boundary line and a first active region of the first standard cell include a distance D1. A first gate line on the first active region protrudes from the first active region by a length L1. The boundary line and a second active region of the second standard cell include a distance D2. A second gate line on the second active region protrudes from the second active region by a length L2. Two first dummy gate lines and two second dummy gate lines are disposed at two sides of the first active region and the second active region and are away from the boundary line by a distance S. The lengths L1 and L2, the distances S, D1 and D2 have the relationships: L1≤D1−S, L2≤D2−S, and D1≠D2.