Latency reduction for transitions between active state and sleep state of an integrated circuit
US12332722B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 24, 2023 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | May 26, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3287
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for efficient power management of multiple integrated circuits. In various implementations, a computing system includes an integrated circuit with a security processor. The security processor determines the integrated circuit transitions to an active state from a sleep state that is not intended to maintain configuration information to return to the active state without restarting an operating system. In the sleep state, multiple components of the integrated circuit have a power supply reference level turned off, which provides low power consumption for the integrated circuit. The security processor performs the bootup operation using information stored in persistent on-chip memory. By not using information stored in off-chip memory, the security processor reduces the latency of the transition. The persistent on-chip memory utilizes synchronous random-access memory that receives a standby power supply reference level that continually supplies a voltage magnitude by not being turned off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.