Pipelined hardware error classification and handling
US12332732B2 · kind B2 · utility
0Cited by
7References
20Claims
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Key dates
| Filing date | Dec 8, 2022 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Apr 6, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0793
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies for detecting and classifying errors detected in pipelined hardware are described. One device includes a hardware pipeline with a set of pipeline stages. Error detection logic can detect an error in the hardware pipeline, and control logic can classify the error in one of the multiple categories based on a type of the error, a position of the first data in a data stream that triggered the error, and a position of a pipeline stage in which the error is detected. The control logic can perform an error-response action based on the error classification of the error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.