Determining an error handling mode
US12332733B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2023 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Jun 14, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0745
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first circuitry may have a first interface. A response circuitry having a system interface may connect to the first circuitry. The response circuitry may receive an input selection that determines an error handling mode used to respond to an error (e.g., in a lockstep system, the error could be a difference between an output at the first interface and a second output at a second interface identified by comparing the first output to the second output). In some implementations, the error handling mode may cause the response circuitry to provide the output to the system interface and send an indication to software based on detecting the error. In some implementations, the error handling mode may cause the response circuitry to contain at least a portion of the output by disabling at least a portion of the system interface for multiple clock cycles based on detecting the error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.