Delayed cache writeback instructions for improved data sharing in manycore processors
US12333305B2 · kind B2 · utility
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5References
14Claims
0Family size
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Key dates
| Filing date | Sep 26, 2020 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | May 15, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus relating to one or more delayed cache writeback instructions for improved data sharing in manycore processors are described. In an embodiment, a delayed cache writeback instruction causes a cache block in a modified state in a Level 1 (L1) cache of a first core of a plurality of cores of a multi-core processor to a Modified write back (M.wb) state. The M.wb state causes the cache block to be written back to LLC upon eviction of the cache block from the L1 cache. Other embodiments are also disclosed and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.