Base plus offset addressing for load/store messages
US12333310B2 · kind B2 · utility
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2References
20Claims
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Key dates
| Filing date | Mar 28, 2024 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Mar 28, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments described herein provide a technique to decompose 64-bit per-lane virtual addresses to access a plurality of data elements on behalf of a multi-lane parallel processing execution resource of a graphics or compute accelerator. The 64-bit per-lane addresses are decomposed into a base address and a plurality of per-lane offsets for transmission to memory access circuitry. The memory access circuitry then combines the base address and the per-lane offsets to reconstruct the per-lane addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.