Power loss reduction in data storage arrays
US12334146B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2023 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Sep 25, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit including a storage array circuit and a control circuit is disclosed. The control circuit may select a particular row of storage circuits in the storage array circuit and activate a first-stage circuit in a particular storage circuit in the particular row by coupling the first-stage circuit to a power supply node. At a later point in time, the control circuit may initiate a transfer of write data from the first-stage circuit to a second-stage circuit in the particular storage circuit and de-activate the first-stage circuit by de-coupling the first-stage circuit from the power supply node. Additionally, the control circuit may also de-select the particular row, at a different point in time, and maintain a de-activated state of the first-stage circuit until a subsequent selection of the particular row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.