Patent · US Active

Link evaluation for a memory device

US12334172B2 · kind B2 · utility

0Cited by

9References

20Claims

0Family size

Assignee

Micron Technology, Inc. · US

Inventors

Markus Balb · Munich, DE
Thomas Hein · Hersbruck, DE
Heinz Hoenigschmid · Starnberg, DE

Key dates

Filing date	Feb 22, 2023
Grant date	Jun 17, 2025
Priority date	—
Expiry date	Sep 7, 2043

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/2254
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Methods, systems, and devices for link evaluation for a memory device are described. A memory device may receive signaling over a channel and may identify logic values encoded into the signaling based on sampling the signaling against a reference voltage. The sampling may occur at a reference time within a sampling period. To evaluate a quality (e.g., margin of error) of the channel, the memory device may adjust the reference voltage, the reference time, or both, and either the memory device or the host device may determine whether the memory device is still able to correctly identify logic values encoded into signaling over the channel. In some cases, the channel quality may be evaluated during a refresh cycle or at another opportunistic time for the memory device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.