Integrated circuit, system and method of forming the same
US12334178B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2023 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Sep 16, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell includes a first, second, third, and fourth transistor, a first and a second inverter, and a first and second word line. The first inverter is coupled to the first and third transistor. The second inverter is coupled to the first inverter and the first and third transistor. The first word line is configured to supply a first word line signal, is on a first metal layer above a front-side of a substrate, and is coupled to the first and third transistor. The second word line is configured to supply a second word line signal, and is on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate, and is coupled to the second and fourth transistor. At least the first, second, third or fourth transistor are on the front-side of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.