Page buffer, memory device, and method for programming thereof
US12334182B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2023 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Aug 20, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A page buffer includes a first charge/discharge circuit and a second charge/discharge circuit coupled to a bit line. The first charge/discharge circuit is configured to store first bit line forcing information and apply a first bit line forcing voltage to the bit line based on the first bit line forcing information. The second charge/discharge circuit coupled to the bit line and configured to store a second bit line forcing information, and apply a second bit line forcing voltage, different from the first bit line forcing voltage, to the bit line based on the second bit line forcing information. The first bit line forcing voltage and the second bit line forcing voltage are both higher than a programming bit line voltage and lower than a programming-inhabit bit line voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.