Power reduction in a clock buffer of a memory module based upon memory module topology
US12334187B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2023 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Aug 27, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/222
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock buffer device for a memory module includes a first clock input coupled to an input of a first phase-locked loop (PLL), and a second clock input coupled to an input of a second PLL. An output of the first PLL is selectably coupled to clock output buffers, and an output of the second PLL is selectably coupled to a subset of the clock output buffers. The clock buffer device receives a first indication that a first information handling system is configured to provide a first clock signal on the first clock input but to not provide a second clock signal on the second clock input, and, in response to the indication, couples the output of the first PLL to the clock output buffers and to disables the second PLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.