Structures and methods for fabricating staircase regions of a three-dimensional NAND memory device
US12334399B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2021 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Sep 4, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method for fabricating a semiconductor device, a stack of alternating insulating layers and sacrificial layers are formed over a substrate. A staircase having a plurality of steps are formed in the stack. Each of the steps has a tread and a riser and further includes a respective pair of the insulating layer and the sacrificial layer over the insulating layer of the respective step. A dielectric layer is formed along the treads and risers of the steps and is doped with one or a combination of carbon, phosphorous, boron, arsenic, and oxygen. The sacrificial layers are further replaced with a conductive material to form word line layers that are arranged between the insulating layers. A plurality of word line contacts are formed to extend from the word line layers of the plurality of steps, and further extend through the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.