Methods and apparatus to reduce defects in interconnects between semicondcutor dies and package substrates
US12334422B2 · kind B2 · utility
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24Claims
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Key dates
| Filing date | Sep 24, 2021 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Sep 22, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L25/0655
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes an array of bumps to electrically couple the die to the substrate. Each of the bumps have a corresponding base. Different ones of the bases have different widths that vary spatially across the array of bumps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.