Memory and forming method thereof
US12336167B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 3, 2022 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | Jan 5, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
The present disclosure relates to a memory and a forming method thereof. The method of forming a memory includes: forming a stacked layer on a surface of a substrate, the stacked layer including interlayer isolation layers arranged at intervals in a first direction and a sacrificial layer group located between adjacent two of the interlayer isolation layers, the sacrificial layer group including a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer sequentially stacked in the first direction, and the stacked layer including a transistor region, where the first direction is a direction perpendicular to a top surface of the substrate; removing the second sacrificial layer in the transistor region to form a first gap; and forming a gate layer and a channel layer wrapping the gate layer in the first gap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.