Semiconductor device structure and methods of forming the same
US12336272B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 2022 |
| Grant date | Jun 17, 2025 |
| Priority date | — |
| Expiry date | May 18, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device structure is provided. The method includes forming semiconductor fins at a first conductivity type region and a second conductivity type region of a substrate, forming a sacrificial gate structure across a portion of the semiconductor fins, wherein the sacrificial gate structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer over the sacrificial gate dielectric layer, and the sacrificial gate dielectric layer on the semiconductor fins of the first conductivity type region is asymmetrical in thickness between a top and a sidewall of the semiconductor fins. The method also includes forming a gate spacer on opposite sidewalls of the sacrificial gate structure, recessing the semiconductor fins not covered by the sacrificial gate structure and the gate spacer, forming source/drain feature on the recessed semiconductor fins, and removing the sacrificial gate structure to expose the top of the semiconductor fins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.