Handling interrupts from a virtual function in a system with a reconfigurable processor
US12340195B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2023 |
| Grant date | Jun 24, 2025 |
| Priority date | — |
| Expiry date | Jun 13, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system is presented that includes a communication link, a runtime processor coupled to the communication link, and a reconfigurable processor. The reconfigurable processor is adapted for generating an interrupt to the runtime processor in response to a predetermined event and includes multiple arrays of coarse-grained reconfigurable (CGR) units and an interface to the communication link that couples the reconfigurable processor to the runtime processor via the communication link. The runtime processor is adapted for configuring the interface to the communication link to provide access to the multiple arrays of coarse-grained reconfigurable units from a physical function driver and from at least one virtual function driver, and the reconfigurable processor is adapted for sending the interrupt to the physical function driver and to a virtual function driver of the at least one virtual function driver within the runtime processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.