Sparse SIMD cross-lane processing unit
US12340227B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2024 |
| Grant date | Jun 24, 2025 |
| Priority date | — |
| Expiry date | Mar 6, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30036
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of the disclosure are directed to a cross-lane processing unit (XPU) for performing data-dependent operations across multiple data processing lanes of a processor. Rather than implementing operation-specific circuits for each data-dependent operation, the XPU can be configured to perform different operations in response to input signals configuring individual operations performed by processing cells and crossbars arranged as a stacked network in the XPU. Each processing cell can receive and process data across multiple data processing lanes. Aspects of the disclosure include configuring the XPU to use a vector sort network to perform a duplicate count eliminating the need to configure the XPU separately for sorting and duplicate counting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.