Partial sum management and reconfigurable systolic flow architectures for in-memory computation
US12340304B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2021 |
| Grant date | Jun 24, 2025 |
| Priority date | — |
| Expiry date | Apr 25, 2044 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for performing machine learning tasks, and in particular, to a neural-network-processing architecture and circuits for improved handling of partial accumulation results in weight-stationary operations, such as operations occurring in compute-in-memory (CIM) processing elements (PEs). One example PE circuit for machine learning generally includes an accumulator circuit, a flip-flop array having an input coupled to an output of the accumulator circuit, a write register, and a first multiplexer having a first input coupled to an output of the write register, having a second input coupled to an output of the flip-flop array, and having an output coupled to a first input of the first accumulator circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.