Chip package structure, preparation method, and electronic device
US12341116B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2021 |
| Grant date | Jun 24, 2025 |
| Priority date | — |
| Expiry date | Jun 16, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package structure includes a glass substrate, a routing layer, and a plurality of dies. A first surface of the glass substrate has solder joints and a second surface of the glass substrate has substrate solder balls. The routing layer is located in the glass substrate, and the solder joints are electrically connected to the substrate solder balls by using the routing layer. Each die has chip solder balls, is located on the first surface of the glass substrate, and the solder joints are bonded to the chip solder balls. The embodiments can improve connection reliability between the die and the glass substrate and can reduce a signal transmission loss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.