Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions

US12342612B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Leonard P. GULER · Hillsboro, US
• Biswajeet Guha · Hillsboro, US
• Tahir Ghani · Portland, US
• Swaminathan Sivakumar · Portland, US

Key dates

• Filing date: Nov 16, 2023
• Grant date: Jun 24, 2025
• Expiry date: Nov 16, 2043

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6219

Abstract

Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, and methods of fabricating neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires, and second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.