Performing instruction fetch pipeline synchronization (IFPS) in processor-based devices
US12346264B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2023 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Jan 4, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Performing instruction fetch pipeline synchronization (IFPS) in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device provides multiple processors including a remote processor. The remote processor receives, from an issuing processor, a translation lookaside buffer (TLB) invalidation (TLBI) request indicating a request to invalidate an address translation, and subsequently receives an IFPS request from the issuing processor. The remote processor determines that any previously received TLBI requests including the most recent TLBI request have completed. Upon receiving the IFPS request, the remote processor determines that all instructions within a fetch pipeline portion that were potentially fetched using address translations older than the IFPS request have proceeded from the fetch pipeline portion of an instruction processing circuit to an execution pipeline portion of the instruction processing circuit. The remote processor then performs a data synchronization barrier (DSB) operation, and issues a synchronization acknowledgement to the issuing processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.