Enabling secure state-clean during configuration of partial reconfiguration bitstreams on FPGA
US12346489B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2023 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Jun 8, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/0841
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus to facilitate enabling secure state-clean during configuration of partial reconfiguration bitstreams on accelerator devices is disclosed. The apparatus includes a security engine to perform, as part of a PR configuration sequence for a new partial reconfiguration (PR) persona corresponding to a PR bitstream, a first clear operation to clear previously-set persona configuration bits in the region; perform, as part of the PR configuration sequence subsequent to the first clear operation, a set operation to set new persona configuration bits in the region; and perform, as part of the PR configuration sequence, a second clear operation to clear memory blocks of the region that became unfrozen subsequent to the set operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.