Patent · US Active

Systems and methods for managing interrupt priority levels

US12346722B2 · kind B2 · utility

0Cited by

1References

20Claims

0Family size

Assignee

MICROCHIP TECHNOLOGY INCORPORATED · US

Inventors

Michael Catherwood · Georgetown, US
Howard Henry Schlunder · Mesa, US
David Mickey · Chandler, US

Key dates

Filing date	Dec 1, 2022
Grant date	Jul 1, 2025
Priority date	—
Expiry date	Apr 3, 2044

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/4818
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A system includes non-transitory computer readable memory and a processor. The non-transitory computer readable memory stores a current processor interrupt priority level and a current disable interrupt control (DISICTL) interrupt priority level. The processor to update the current processor interrupt priority level based on respective interrupt priority levels associated with respective exceptions, and update the current DISICTL interrupt priority level based on a respective DISICTL instruction, wherein the respective DISICTL instruction specifies a respective user-definable DISICTL interrupt priority level. The processor determines a highest interrupt priority level between the current processor interrupt priority level and the current DISICTL interrupt priority level, and apply the highest interrupt priority level during execution of respective code.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.