On-chip performance throttling
US12347494B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2023 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Jan 9, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory block with memory cells that are arranged in word lines. Control circuitry in the memory device selects a word line to program; sets a programming pulse voltage to a starting value; and determines an operating temperature and compares the operating temperature to a first threshold temperature. In response to the operating temperature being less than the first threshold temperature, the control circuitry sets a program voltage step size to a baseline. In response to the operating temperature being greater than a first threshold temperature, the control circuitry sets the program voltage step size to a high temperature step size that is less than the baseline step size. The control circuitry programs the selected word line. Each program loop includes a programming pulse, and the control circuitry increases a magnitude of the programming pulse between program loops by the program voltage step size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.