NAND early erase termination based on leakage current test
US12347497B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2022 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Feb 16, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technology is disclosed herein for early erase termination as a counter-measure for erase disturb. Multiple erase blocks of NAND memory cells are erased in parallel during an erase procedure. Erasing multiple erase blocks in parallel can place considerable strain on the circuitry that generates the erase voltage. If there is significant leakage current in one of the erase blocks the magnitude of the erase voltage for all of the erase blocks may drop. The erase blocks are tested sequentially for leakage current during the first erase loop while the erase voltage is applied to only the erase block under test. If any erase block fails the leakage current test that erase block is removed from the erase procedure. One or more additional erase loops are then performed with only those erase blocks that passed the leakage current test simultaneously receiving an erase voltage, thereby preventing erase disturb with early termination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.