Memory device and operating method of the same
US12347505B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2024 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Apr 29, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is provided, including a first bit cell including a first memory cell coupled to a first word line and a second bit cell including a second memory cell coupled to a second word line. The first and second memory cells are coupled to a first control line and further coupled to a first bit line through first and second nodes. The second bit cell further includes a first protection array coupled to the second memory cell at the second node coupled to the first bit line and further coupled to a third word line. When the first and second bit cells operate in different operational types, the first protection array is configured to generate an adjust voltage to the second node according to a voltage level of the third word line while the first bit cell is programmed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.