Systems and methods for mitigating crack propagation in semiconductor die manufacturing
US12347732B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2023 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Apr 24, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/562
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for mitigating crack propagation during manufacture of semiconductor dies, and associated systems and methods are disclosed herein. The method includes forming holes into a first side of a wafer substrate opposite a second side. The wafer substrate has active components at the second side. Each hole extends from the first side towards the second side an extend to an intermediate depth within the wafer substrate such that a bottom of the holes is spaced vertically apart from the active components on the second side. The holes are configured to inhibit cracks in the wafer substrate from propagating longitudinally across the wafer substrate. The method also includes backgrinding the first side of the wafer substrate to thin the wafer substrate after forming the holes. The method also includes dicing the wafer substrate after backgrinding to separate individual semiconductor dies from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.