Three-dimensional memory devices with drain-select-gate cut structures and methods for forming the same
US12349351B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2022 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Jun 23, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
A method for forming a three-dimensional (3D) memory device includes forming a dielectric stack including a plurality of first/second dielectric layer pairs over a substrate, forming a plurality of channel structures extending in a lateral direction in a core region of the dielectric stack, forming a staircase structure including a plurality of stairs extending along the lateral direction in a staircase region of the dielectric stack, forming a first drain-select-gate (DSG) cut opening extending in the lateral direction in the core region and a second DSG cut opening in the staircase region, and forming a first DSG cut structure in the first DSG cut opening and a second DSG cut structure in the second DSG cut opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.