Isolation structures in semiconductor devices
US12349383B2 · kind B2 · utility
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11References
20Claims
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Key dates
| Filing date | May 6, 2022 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Jun 2, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0142
Abstract
A semiconductor device with different isolation structures and a method of fabricating the same are disclosed. The a method includes forming first and second fin structures on a substrate, forming a dummy fin structure on the substrate and between the first and second fin structures, forming a polysilicon structure on the dummy fin structure, forming source/drain regions on the first and second fin structures, and replacing the polysilicon structure with a dummy gate structure. A top portion of the dummy gate structure is formed wider than a bottom portion of the dummy gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.