Gate-all-around integrated circuit structures having dual nanoribbon channel structures
US12349411B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2023 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Nov 15, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.