Semiconductor device
US12349414B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2022 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Oct 7, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
Abstract
Each first thin film transistor of a semiconductor device includes: a lower electrode; a first oxide semiconductor layer including a channel region and first and second contact regions; a gate electrode disposed on the channel region with a gate insulating layer interposed therebetween; and a source electrode and a drain electrode connected to the first contact region and the second contact region, respectively. When viewed from a normal direction of the substrate, at least a part of the channel region overlaps the lower electrode, and at least one of the first and second contact regions is located outside the lower electrode. The channel region has a layered structure including a lower layer, an upper layer located between the lower layer and the gate insulating layer, and a high mobility layer disposed between the lower layer and the upper layer and having mobility higher than mobility of the lower layer and the upper layer. In the channel region, the thickness of the upper layer is equal to or less than 1/3 of the thickness of the lower layer, and the thickness of the high mobility layer is equal to or less than 1/2 of the thickness of the lower layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.