Wafer testing for current property of a power transistor
US12352801B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2023 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Jan 16, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/14
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Wafer testing of a power transistor for a current property of the power transistor. Wafer testing of a power transistor is performed by using a sense transistor constructed using the same epitaxial stack as was used to construct the power transistor. The current property of the sense transistor is then measured, and the current property of the power transistor can be determined from that measurement. Furthermore, the sense transistor is pre-conditioned prior to the measurement by alternately turning on and off the sense transistor multiple cycles while allowing a source terminal of the power transistor to float. This simulates operating conditions of the power transistor, thereby allowing for measurement of the current property of the power transistor as it would likely be in operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.