Error rate interrupts in hardware for high-speed signaling interconnect
US12353271B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2023 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Dec 1, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A receiver device includes detection logic, error counter logic, and threshold logic. The detection detects frame errors in data frames received by a transmitter device. The error counter logic increments a first value of an error count responsive to each error signal, indicative of a frame error in a data frame, received from the detection logic. The error counter logic reduces the first value to a second value (non-zero value) for the error count responsive to receiving a decrement signal and a period marker signal corresponding to a programmable period. The error counter logic resets the first value or the second value of the error count to zero responsive to receiving a reset signal. The threshold logic compares a current value of the error count with a threshold number of frame errors and output an interrupt responsive to the current value satisfying the threshold number of frame errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.