Single cycle request arbiter
US12353764B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 2, 2023 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Aug 28, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array includes a plurality of memory devices, each of which includes a memory configured to store packet data and a request arbiter configured to interface with other memory devices of the memory array. The request arbiter filters invalid requests from a plurality of requestors, and determines a bitvector representing a sequence of the plurality of requestors, the bitvector indicating whether each of the plurality of requestors has a valid request. The request arbiter outputs an indication of a first request to be serviced by the memory device, and shifts the bitvector to determine a second request to be serviced by the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.