Transformations for multicycle path prediction of clock signals
US12353809B2 · kind B2 · utility
0Cited by
7References
20Claims
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Key dates
| Filing date | May 26, 2022 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Mar 14, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Emulating a circuit design includes remodeling the clock signals of the circuit design. A circuit design includes clock signals that are based on a root clock signal. The clock signals are analyzed to identify a first clock signal of the clock signals that is faster than a second clock signal of the clock signals. The second clock signal is remodeled based on the first clock signal. An updated circuit design is generated based on remodeled second clock signal, and operation of the updated circuit design is emulated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.